	US 12,362,180 B2
	Method of manufacturing semiconductor devices
Chin-Ta Chen, Hsinchu (TW); Hua-Tai Lin, Hsinchu (TW); Han-Wei Wu, Tainan (TW); and Jiann-Yuan Huang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 14, 2024, as Appl. No. 18/605,141.
Application 18/605,141 is a continuation of application No. 17/175,366, filed on Feb. 12, 2021, granted, now 11,961,738.
Prior Publication US 2024/0234143 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/027 (2006.01); H01L 21/3213 (2006.01)

CPC H01L 21/0274 (2013.01) [H01L 21/32139 (2013.01)]

20 Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a first hard mask layer over a target layer to be patterned;

forming a photo resist layer over the first hard mask layer;

patterning the photo resist layer;

etching the first hard mask layer using the patterned photo resist layer as an etching mask to form first etched portions of the first hard mask layer;

forming a second hard mask layer over the patterned photo resist layer and the first hard mask layer,

wherein the second hard mask layer fills the first etched portions of the first hard mask layer;

planarizing the second hard mask layer to expose an upper surface of the first hard mask layer and form a second hard mask layer pattern; and

etching exposed portions of the first hard mask layer and the target layer using the second hard mask layer pattern as an etching mask.

9. A method of manufacturing a semiconductor device, comprising:

patterning a photo resist layer to form photo resist pattern over an underlying layer,

wherein the photo resist pattern includes resist scum between adjacent photo resist pattern features;

forming a hard mask layer over the photo resist pattern,

wherein the hard mask layer includes a seam or void extending along a first direction between the adjacent photo resist pattern features of the photo resist pattern and a recess located at an end of the seam or void along the first direction,

wherein the recess is located at a greater distance from the underlying layer along the first direction than an uppermost surface of the photo resist pattern;

exposing an upper portion of the photo resist pattern;

forming a hard mask pattern by etching exposed portions of the photo resist pattern using the hard mask pattern as an etching mask; and

patterning the underlying layer using the hard mask pattern as an etching mask.

16. A method of manufacturing a semiconductor device, comprising:

forming a photo resist layer over an underlying layer disposed over a semiconductor substrate;

determining an optimum dose amount of actinic radiation to form a pattern in the photo resist layer exposing the underlying layer;

selectively exposing the photo resist layer to an exposure dose amount of actinic less than the optimum dose amount,

wherein the exposure dose amount is 10% to 40% less than the optimum dose amount;

developing the exposed photo resist layer to form a photo resist pattern;

forming a hard mask layer over the photo resist pattern;

removing a portion of the hard mask layer to expose an upper portion of the photo resist pattern;

forming a hard mask pattern by removing the photo resist pattern; and

etching the underlying layer by using the hard mask pattern as an etching mask.