US 12,362,034 B2
Semiconductor device related to a parallel test
Hyun Seung Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 22, 2023, as Appl. No. 18/453,903.
Claims priority of application No. 10-2023-0066484 (KR), filed on May 23, 2023.
Prior Publication US 2024/0395353 A1, Nov. 28, 2024
Int. Cl. G11C 29/54 (2006.01)
CPC G11C 29/54 (2013.01) 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an even data input circuit configured to store, in an even core cell, data input through an even data pad and including a first pattern in response to an even data input strobe signal during a write operation of a parallel test; and
an odd data input circuit configured to store, in an odd core cell, data input through the even data pad and including a second pattern in response to an odd data input strobe signal during the write operation of the parallel test; and
a comparison code generation circuit configured to compare data output from the even core cell and data output from the odd core cell during a read operation of the parallel test and to output a comparison code used to detect a fail in the data output from the even core cell or the data output from the odd core cell.