US 12,362,023 B2
Semiconductor memory device
Hideki Igarashi, Kawasaki Kanagawa (JP); and Tomokazu Nakai, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 2, 2022, as Appl. No. 17/902,744.
Claims priority of application No. 2022-024627 (JP), filed on Feb. 21, 2022.
Prior Publication US 2023/0268012 A1, Aug. 24, 2023
Int. Cl. G11C 16/14 (2006.01); G06F 7/57 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3445 (2013.01) [G06F 7/57 (2013.01); G11C 16/14 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a plurality of conductive layers arranged in a first direction intersecting with a surface of the substrate;
a first semiconductor layer that extends in the first direction and is opposed to the plurality of conductive layers;
an electric charge accumulating layer disposed between the plurality of conductive layers and the first semiconductor layer;
a first wiring connected to one end portion in the first direction of the first semiconductor layer; and
a control circuit electrically connected to the plurality of conductive layers and the first wiring,
wherein:
the control circuit is configured to be able to perform an erase operation,
the erase operation includes a plurality of erase loops,
each of the plurality of erase loops includes:
an erase voltage supply operation that applies an erase voltage to the first wiring;
a first erase verify operation that applies a read pass voltage smaller than the erase voltage to a first conductive layer among the plurality of conductive layers, and applies an erase verify voltage smaller than the read pass voltage to a second conductive layer among the plurality of conductive layers after performing the erase voltage supply operation; and
a second erase verify operation that applies the erase verify voltage to the first conductive layer, and applies the read pass voltage to the second conductive layer after performing the first erase verify operation,
the erase voltage increases by a first offset voltage in each erase loop from a first erase loop to an a-th erase loop, where a is an integer of 2 or more,
the erase voltage increases by a second offset voltage in each erase loop from an a+1-th erase loop to a b-th erase loop, where b is an integer of a+2 or more,
the second offset voltage is larger than the first offset voltage,
the erase voltage is applied to the first wiring for a first application period in each erase loop from the first erase loop to the a-th erase loop,
the erase voltage is applied to the first wiring for a second application period in each erase loop from the a+1-th erase loop to the b-th erase loop, and
the second application period is longer than the first application period.