| CPC G11C 16/26 (2013.01) [G11C 5/06 (2013.01)] | 20 Claims |
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1. A semiconductor memory comprising:
a memory cell;
a bit line electrically connected to the memory cell;
a sense amplifier in a first circuit area and including a first latch circuit;
a first hookup circuit in a second circuit area and configured to control connection between the bit line and the sense amplifier;
a second latch circuit;
a first wiring connected between the first latch circuit and the second latch circuit; and
a first pre-charge circuit including a first transistor in a third circuit area between the first circuit area and the second circuit area, the first transistor having a first end connected to the first wiring at a first position in the third circuit area and a second end connectable to a terminal that is supplied with one of a pre-charge voltage and a ground voltage.
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