US 12,362,020 B2
Semiconductor memory device having a control circuit for changing a drive capability of an output circuit of the semiconductor memory device
Shouichi Ozaki, Tokyo (JP); Kazuhiko Satou, Yokohama Kanagawa (JP); Kenro Kubota, Fujisawa Kanagawa (JP); Fumiya Watanabe, Chigasaki Kanagawa (JP); Atsuko Saeki, Yokohama Kanagawa (JP); Ryota Tsuchiya, Kamakura Kanagawa (JP); Harumi Abe, Kawasaki Kanagawa (JP); and Toshifumi Watanabe, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 28, 2023, as Appl. No. 18/176,442.
Claims priority of application No. 2022-138948 (JP), filed on Sep. 1, 2022.
Prior Publication US 2024/0079067 A1, Mar. 7, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
an output pin configured for connection with a memory controller;
an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller;
a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin;
a reference voltage line connected to the output circuit; and
a detection circuit configured to detect a voltage fluctuation in the reference voltage line,
wherein the control circuit sets a parameter for changing the drive capability of the output circuit based on the detected voltage fluctuation.