US 12,362,017 B2
Memory device with reduced area
Chun-Ying Lee, Hsinchu (TW); Chia-En Huang, Xinfeng Township (TW); and Chieh Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 11, 2024, as Appl. No. 18/632,856.
Application 18/632,856 is a continuation of application No. 17/752,662, filed on May 24, 2022, granted, now 11,984,165.
Prior Publication US 2024/0257877 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01)
CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of word lines (WLs) above a substrate;
a plurality of memory strings laterally isolated from each other, wherein each of the plurality of memory strings is operatively coupled to a respective subset of the plurality of WLs; and
a plurality of drivers each configured to control a corresponding one of the plurality of WLs and comprising a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.