US 12,362,015 B2
Memory array structure
Gerben Doornbos, Kessel-Lo (BE)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Apr. 27, 2022, as Appl. No. 17/730,350.
Prior Publication US 2023/0352089 A1, Nov. 2, 2023
Int. Cl. G11C 16/04 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a dielectric layer overlying a semiconductor substrate;
a first plurality of control gates embedded in the dielectric layer, wherein a control gate of the first plurality of control gates is part of a memory cell of a non-volatile memory array;
a channel layer overlying the dielectric layer, wherein a charge storing component of the memory cell separates the channel layer from the control gate of the first plurality of control gates;
a plurality of contacts in contact with the channel layer; and
a second plurality of control gates overlying the channel layer, wherein a control gate of the second plurality of control gates overlies a region between two adjacent control gates of the first plurality of control gates.