US 12,362,014 B2
In-memory computing (IMC) memory device and in-memory computing method
Yu-Yu Lin, New Taipei (TW); and Feng-Min Lee, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Apr. 20, 2023, as Appl. No. 18/303,726.
Prior Publication US 2024/0355387 A1, Oct. 24, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0061 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An in-memory computing (IMC) memory device, comprising:
a plurality of computing memory cells, the plurality of computing memory cells forming a plurality of memory strings, the plurality of computing memory cells storing a plurality of weight values;
a loading capacitor coupled to the plurality of computing memory cells; and
a measurement circuit coupled to the loading capacitor,
wherein in a plurality of IMC operations performed by the IMC memory device,
a plurality of input voltages are input into the plurality of computing memory cells, the plurality of input voltages being corresponding to a plurality of input values,
a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values,
when a read voltage is applied to the plurality of computing memory cells, the plurality of computing memory cells are configured to generate a plurality of cell currents, the plurality of cell currents are summed into a plurality of memory string currents,
the plurality of memory strings are configured to charge the loading capacitor with the plurality of memory string currents,
the measurement circuit is configured to measure a capacitor voltage of the loading capacitor, and
based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the plurality of input values and the plurality of weight values is determined.