US 12,362,012 B2
Mixed bitline lockout for QLC/TLC die
Xiang Yang, Santa Clara, CA (US); and Hua-Ling Cynthia Hsu, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,304.
Prior Publication US 2024/0071482 A1, Feb. 29, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more control circuits configured to connect to a memory structure comprising NAND memory cells, wherein the memory structure further comprises bit lines associated with the NAND memory cells, wherein the one or more control circuits are configured to:
load n−1 pages of user data into a first n−1 pages of data latches and a default page into one page of data latches, wherein a total of n pages of data latches are loaded, wherein n is an integer greater than two, wherein n bits of state information are loaded for each memory cell in a group of memory cells, wherein the default page comprises the same bit value for all memory cells in the group;
program the user data into the group of the memory cells based on the n bits of state information in the n pages of data latches prior to a pre-determined data state completing verification, including perform a no-lockout program verify;
re-arrange content in the first n−1 pages of data latches into a second n−1 pages of data latches after the pre-determined data state completes verification, wherein n−1 bits of state information are stored for each memory cell in the group; and
program the user data into the group based on the n−1 bits of state information in the second n−1 pages of data latches after the pre-determined data state completes verification, including perform a lockout verify.