US 12,362,010 B2
Memory circuit and method of operating same
Luping Kong, Hsinchu (TW); Chia-Cheng Chen, Hisnchu (TW); Ching-Wei Wu, Hsinchu (TW); and Jun Xie, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed on Jul. 26, 2023, as Appl. No. 18/359,169.
Claims priority of application No. 202310782406.9 (CN), filed on Jun. 29, 2023.
Prior Publication US 2025/0006255 A1, Jan. 2, 2025
Int. Cl. G11C 11/00 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a word line driver circuit coupled to a word line; and
a control circuit coupled to the word line driver circuit, and configured to delay a leading edge or a falling edge of a word line signal in response to at least a first clock signal, the control circuit comprising:
a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal; and
an adjustable delay circuit configured to receive a first supply voltage and a second supply voltage, and configured to adjust a delay between the second clock signal and a third clock signal in response to the second clock signal and an enable signal, the third clock signal being a delayed version of the second clock signal,
wherein an amount of the delay between the second clock signal and the third clock signal is based on a voltage difference between the first supply voltage and the second supply voltage, the first supply voltage having a first swing, and the second supply voltage having a second swing.