US 12,362,009 B2
SRAM performance optimization via transistor width and threshold voltage tuning
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 16, 2023, as Appl. No. 18/336,304.
Application 18/336,304 is a continuation of application No. 17/377,175, filed on Jul. 15, 2021, granted, now 11,682,450.
Prior Publication US 2023/0326519 A1, Oct. 12, 2023
Int. Cl. G11C 11/412 (2006.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/412 (2013.01) [G11C 11/419 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of active regions that each extend in a first horizontal direction in a top view; and
a plurality of gate structures that each extend in a second horizontal direction in the top view;
wherein:
the plurality of active regions and the plurality of gate structures are components of an electronic memory device; and
at least a subset of the active regions have different dimensions in the second horizontal direction than a rest of the active regions.