US 12,362,007 B2
Memory controller support for mixed read
Rasmus Madsen, Copenhagen (DK); Lunkai Zhang, Portland, OR (US); and Martin Lueker-Boden, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 27, 2023, as Appl. No. 18/360,096.
Claims priority of provisional application 63/505,784, filed on Jun. 2, 2023.
Prior Publication US 2024/0404582 A1, Dec. 5, 2024
Int. Cl. G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a communication interface configured to connect to read circuitry that is configured to read memory cells, the read circuitry configured to perform a first type of read having a first performance time and a second type of read having a second performance time that is longer than the first performance time; and
one or more control circuits coupled to the communication interface, the one or more control circuits configured to:
track expected usage of the communication interface to return data by the read circuitry in response to read commands of the first type and the second type, wherein the first type of read command has a first data out latency and the second type of read command has a second data out latency that is longer than the first data out latency; and
control timing of issuance of read commands of the first type and the second type to meet a timing constraint for data returned from the read circuitry on the communication interface.