US 12,362,005 B2
Semiconductor memory device
Masakazu Kakumu, Tokyo (JP); Koji Sakui, Tokyo (JP); and Nozomu Harada, Tokyo (JP)
Assigned to UNISANTIS ELECTRONICS SINGAPORE PTE. LTD., Singapore (SG)
Filed by Unisantis Electronics Singapore Pte. Ltd., Singapore (SG)
Filed on Jun. 8, 2023, as Appl. No. 18/331,328.
Claims priority of application No. PCT/JP2022/023426 (WO), filed on Jun. 10, 2022.
Prior Publication US 2023/0402089 A1, Dec. 14, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01)
CPC G11C 11/4096 (2013.01) [H10B 12/20 (2023.02); H10D 30/6735 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A memory device with semiconductor elements, comprising:
a semiconductor base material extending on a substrate in a horizontal direction or a vertical direction;
a first impurity region and a second impurity region that are continuous with respective opposite ends of the semiconductor base material;
a first gate insulating layer partially covering the semiconductor base material;
a first gate conductor layer covering the first gate insulating layer;
a second gate insulating layer continuous with the first gate insulating layer and partially covering the semiconductor base material; and
a second gate conductor layer not in contact with the first gate conductor layer, the second gate conductor layer covering the second gate insulating layer,
wherein a memory erase operation is performed by applying to one of the first gate conductor layer and the second gate conductor layer a first voltage in a range of 0 V to a threshold voltage, and also applying to the other of the first gate conductor layer and the second gate conductor layer a second voltage having a polarity identical to a polarity of the first voltage and having an absolute value greater than or equal to an absolute value of the threshold voltage, thereby reducing holes or electrons that are majority carriers remaining in the semiconductor base material.