US 12,362,004 B2
Scaled 2T DRAM
Min Gyu Sung, Latham, NY (US); Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Chanro Park, Clifton Park, NY (US); and Juntao Li, Cohoes, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on May 19, 2023, as Appl. No. 18/320,234.
Prior Publication US 2024/0386943 A1, Nov. 21, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 11/4096 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC G11C 11/4096 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor,
wherein a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via, and wherein a channel region of the vertical transistor comprises indium-gallium-zinc-oxide (IGZO).