US 12,362,003 B2
In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders
Yu-Hsuan Lin, Taichung (TW); Po-Hao Tseng, Taichung (TW); Feng-Min Lee, Hsinchu (TW); and Ming-Hsiu Lee, Hsinchu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2023, as Appl. No. 18/303,194.
Application 18/303,194 is a continuation of application No. 17/344,555, filed on Jun. 10, 2021, granted, now 11,664,070.
Claims priority of provisional application 63/142,976, filed on Jan. 28, 2021.
Prior Publication US 2023/0253032 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4093 (2006.01); G06F 7/501 (2006.01); G06F 7/523 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4093 (2013.01) [G06F 7/501 (2013.01); G06F 7/523 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An in-memory computation method, comprising:
providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values;
respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer;
providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and
performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.