US 12,362,002 B2
Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array
Rifat Ferdous, Lafayette, IN (US); Sung-Taeg Kang, Palo Alto, CA (US); Rohit S. Shenoy, Fremont, CA (US); Ali Khakifirooz, Brookline, MA (US); and Dipanjan Basu, Portland, OR (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on May 17, 2021, as Appl. No. 17/322,724.
Prior Publication US 2022/0366962 A1, Nov. 17, 2022
Int. Cl. G11C 16/08 (2006.01); G11C 7/04 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 7/04 (2013.01); G11C 11/4074 (2013.01); G11C 11/409 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for reading a NAND device, comprising:
reading a 3D (three dimensional) NAND device having a 3D stack with multiple wordlines vertically stacked, including setting the multiple wordlines to a high voltage bias, wherein the multiple wordlines include a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline;
transitioning a selected wordline of the multiple wordlines from the high voltage bias to ground, wherein the selected wordline is a selected middle wordline of the middle wordlines, the selected middle wordline being a critical wordline having a higher sensitivity to temperature change than other wordlines in the 3D stack;
delaying a transitioning of other wordlines of the multiple wordlines from the high voltage bias to ground relative to the transitioning of the selected wordline of the multiple wordlines from the high voltage bias to ground; and
transitioning the other wordlines from the high voltage bias to ground after the delaying.