US 12,362,000 B2
Memory device and operating method thereof
Jun-Cheng Liu, Nanjing (CN); Zhi-Min Zhu, Nanjing (CN); Chien-Yu Huang, Taoyuan (TW); and Ching-Wei Wu, Nantou County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW); and TSMC Nanjing Company Limited, Jiangsu Province (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC Nanjing Company Limited, Nanjing (CN)
Filed on Aug. 2, 2023, as Appl. No. 18/364,094.
Claims priority of application No. 202321785271 (CN), filed on Jul. 7, 2023.
Prior Publication US 2025/0014631 A1, Jan. 9, 2025
Int. Cl. G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4074 (2013.01) [G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
at least one bit cell coupled to at least one of a plurality of data lines;
a pair of transistors, first terminals of the pair of transistors being coupled to the plurality of data lines respectively, second terminals of the pair of transistors being coupled to a negative voltage line; and
a voltage generation circuit coupled to the negative voltage line and configured to pull down a voltage of the at least one of the plurality of data lines to a negative voltage level through the negative voltage line, the voltage generation circuit comprising:
a first capacitive unit comprising a first capacitor;
a second capacitive unit comprising a second capacitor; and
a switch circuit coupled between the first capacitive unit and the negative voltage line and between the second capacitive unit and the negative voltage line, and configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.