US 12,361,998 B2
Sustainable DRAM having principle power supply voltage unified with logic circuit
Chao-Chun Lu, Taipei (TW); Bor-Doou Rong, Zhubei (TW); and Chun Shiah, Hsinchu (TW)
Assigned to Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG); and Etron Technology, Inc., Hsinchu (TW)
Filed by ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed on May 28, 2021, as Appl. No. 17/333,836.
Application 17/333,836 is a continuation in part of application No. 16/354,187, filed on Mar. 15, 2019, granted, now 11,302,383.
Claims priority of provisional application 62/777,727, filed on Dec. 10, 2018.
Prior Publication US 2021/0295893 A1, Sep. 23, 2021
Int. Cl. G11C 11/4074 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4074 (2013.01) [G11C 11/4096 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A DRAM chip configured to couple with an external logic circuit chip and to couple with a principle power supply voltage source, comprising:
a first sustaining voltage generator producing a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM chip; and
a DRAM core circuit with a DRAM cell comprising an access transistor and a storage capacitor;
wherein the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator;
wherein a voltage level of the principle power supply voltage source to the DRAM chip is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit chip, wherein the DRAM chip is physically separate from the external logic circuit chip, the DRAM chip and the external logic circuit chip are two different semiconductor chips, and the voltage level of the principle power supply voltage source to the DRAM chip is not greater than 0.9V, wherein during write operation of the signal ONE to the DRAM cell, the storage capacitor is stored the first voltage level, and the voltage level corresponding to the signal ONE utilized in the DRAM chip is equal to the voltage level of the principle power supply voltage source;
wherein a process node of the external logic circuit chip is smaller than that of the DRAM chip.