US 12,361,994 B2
Semiconductor memory structure and method for forming the semiconductor memory structure
Chih-Chuan Su, Hsinchu (TW); Yu-Jen Wang, Hsinchu (TW); Liang-Wei Wang, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 10, 2022, as Appl. No. 17/571,945.
Prior Publication US 2023/0223063 A1, Jul. 13, 2023
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC G11C 11/161 (2013.01) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor memory structure, comprising:
forming bottom electrodes in a substrate;
depositing a first MTJ material over the bottom electrodes;
patterning and etching the first MTJ material to form first MTJ elements over the bottom electrodes in a first region and a second region in the substrate;
depositing a second MTJ material over the first MTJ elements;
patterning and etching the second MTJ material to form second MTJ elements over the first MTJ elements in the first region and the second region in the substrate; and
forming top electrodes over the second MTJ elements,
wherein the first MTJ elements in the first region are narrower than the first MTJ elements in the second region, wherein bottom widths of the second MTJ elements are greater than top widths of the second MTJ elements.