US 12,361,982 B2
Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode
Harsh Rawat, Haryana (IN); Nitin Chawla, Noida (IN); Promod Kumar, Greater Noida (IN); Kedar Janardan Dhori, Ghaziabad (IN); and Manuj Ayodhyawasi, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Aug. 14, 2023, as Appl. No. 18/233,562.
Claims priority of provisional application 63/402,208, filed on Aug. 30, 2022.
Prior Publication US 2024/0071429 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/1009 (2013.01) [G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 7/109 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
a word line drive circuit for each row having an output connected to drive the word line of the row;
a row decoder circuit coupled to the word line drive circuits;
a control circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory access operation and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during an in-memory computation operation;
an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode;
a computation circuit configured to store feature data and perform a computational operation as a function of the feature data and a plurality of sub-array data bits present at the plurality of bit line inputs to generate a plurality of partial computation data bits; and
a plurality of sub-array data outputs coupled to the computation circuit and configured to output the plurality of partial computation data bits in the second mode.