US 12,361,907 B2
Digital-to-analog converter, data driver, and display device
Hiroshi Tsuchi, Yokohama (JP)
Assigned to LAPIS Technology Co., Ltd., Yokohama (JP)
Filed by LAPIS Technology Co., Ltd., Yokohama (JP)
Filed on Mar. 11, 2024, as Appl. No. 18/601,529.
Prior Publication US 2024/0312428 A1, Sep. 19, 2024
Int. Cl. G09G 3/36 (2006.01); G09G 3/3275 (2016.01)
CPC G09G 3/3688 (2013.01) [G09G 3/3275 (2013.01); G09G 2300/0828 (2013.01); G09G 2300/0838 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A digital-to-analog converter that converts K-bit (K is a positive number of 2 or more) digital data into an analog output voltage and outputs the analog output voltage, comprising:
a differential amplifier that includes a plurality of input terminals and outputs the output voltage having one voltage level corresponding to the K-bit digital data among a voltage level group obtained by dividing a voltage received at the respective plurality of input terminals into a Kth-power of 2 pieces by linear interpolation from own output terminals; and
a first decoder that receives a first voltage and a second voltage and distributes and supplies the first voltage or the second voltage to the respective plurality of input terminals of the differential amplifier based on the K-bit digital data, wherein
the differential amplifier includes:
a Kth-power of 2 pieces of differential pairs each including an inverting input terminal to which the output voltage is input in common, a non-inverting input terminal to which one of voltages received at the plurality of input terminals is supplied as an input voltage, and an output pair, each of the output pairs being connected in common, the Kth-power of 2 pieces of respective differential pairs being driven by an individually received tail current;
an amplification stage that generates the output voltage by an amplification action based on an output of one or both of the output pair of each of the Kth-power of 2 pieces of the differential pairs; and
a tail current control circuit that individually supplies the tail current to each of the Kth-power of 2 pieces of the differential pairs, wherein
the tail current control circuit sets a current ratio to a reference current value in the tail current flowing through respective differential pairs excluding two differential pairs among the Kth-power of 2 pieces of the differential pairs as a predetermined reference value, and
the current ratio of the tail current flowing through the two respective differential pairs is set to a value larger than the reference value.