US 12,361,906 B2
Driver circuit, display device, and electronic device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Nov. 29, 2023, as Appl. No. 18/522,347.
Application 18/522,347 is a continuation of application No. 18/120,489, filed on Mar. 13, 2023, granted, now 11,837,189.
Application 18/120,489 is a continuation of application No. 17/862,464, filed on Jul. 12, 2022, granted, now 11,620,962, issued on Apr. 4, 2023.
Application 17/862,464 is a continuation of application No. 17/190,945, filed on Mar. 3, 2021, granted, now 11,455,968, issued on Sep. 27, 2022.
Application 17/190,945 is a continuation of application No. 16/812,604, filed on Mar. 9, 2020, granted, now 10,971,103, issued on Apr. 6, 2021.
Application 16/812,604 is a continuation of application No. 16/176,016, filed on Oct. 31, 2018, granted, now 10,665,195, issued on May 26, 2020.
Application 16/176,016 is a continuation of application No. 15/062,265, filed on Mar. 7, 2016, granted, now 10,121,435, issued on Nov. 6, 2018.
Application 15/062,265 is a continuation of application No. 14/644,372, filed on Mar. 11, 2015, granted, now 9,311,876, issued on Apr. 12, 2016.
Application 14/644,372 is a continuation of application No. 14/305,367, filed on Jun. 16, 2014, granted, now 9,036,767, issued on May 19, 2015.
Application 14/305,367 is a continuation of application No. 13/675,077, filed on Nov. 13, 2012, granted, now 8,774,347, issued on Jul. 8, 2014.
Application 13/675,077 is a continuation of application No. 12/477,338, filed on Jun. 3, 2009, granted, now 8,314,765, issued on Nov. 20, 2012.
Claims priority of application No. 2008-157400 (JP), filed on Jun. 17, 2008.
Prior Publication US 2024/0169951 A1, May 23, 2024
Int. Cl. G11C 19/28 (2006.01); G09G 3/36 (2006.01); G11C 19/18 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3648 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); G09G 2300/0809 (2013.01); G09G 2310/0286 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel portion comprising a first transistor; and
a signal line driver circuit comprising a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
wherein a gate of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein a gate of the third transistor is electrically connected to a gate of the fifth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the fourth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the fourth wiring,
wherein a gate of the eighth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the fourth wiring,
wherein a gate of the ninth transistor is electrically connected to the gate of the third transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the third transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the fourth wiring,
wherein a gate of the tenth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the third transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to the fourth wiring,
wherein a gate of the eleventh transistor is electrically connected to the sixth wiring,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to the fourth wiring,
wherein a gate of the twelfth transistor is electrically connected to a seventh wiring,
wherein a first output signal is output from the first wiring,
wherein a clock signal is input to the second wiring,
wherein a second output signal is output from the third wiring,
wherein a first potential is input to the fourth wiring,
wherein a first signal is input to the fifth wiring,
wherein a second signal is input to the sixth wiring,
wherein a third signal is input to the seventh wiring,
wherein the third transistor is configured to control a potential of the gate of the first transistor, and
wherein the sixth transistor is configured to control a potential of the gate of the second transistor.