US 12,361,881 B2
Display panel and display device
Xiang Zhou, Guangdong (CN); Weiyao Wei, Guangdong (CN); Baixiang Han, Guangdong (CN); and Guangyao Li, Guangdong (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
Filed on Jan. 31, 2024, as Appl. No. 18/428,742.
Claims priority of application No. 202311729718.X (CN), filed on Dec. 14, 2023.
Prior Publication US 2025/0201188 A1, Jun. 19, 2025
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A display panel comprising a display portion and a gate driver circuit located at a side of the display portion, wherein the display portion comprises a plurality of sub-pixel rows, each of the plurality of sub-pixel rows comprises a plurality of sub-pixel units, and a pixel circuit is provided in each of the plurality of sub-pixel units,
wherein each of the pixel circuits comprises a switching transistor, a driver transistor, a first reset transistor and a second reset transistor, the switching transistor is connected to the driver transistor via a first reset node, the first reset transistor is connected to the driver transistor via the first reset node, and the second reset transistor is connected to the driver transistor via a second reset node,
wherein the gate driver circuit comprises a plurality of gate driver units connected in cascade, each of the plurality of gate driver units comprises a first signal output terminal and a second signal output terminal, a gate of the switching transistor of the pixel circuit in a b-th row of the sub-pixel rows is connected to the second signal output terminal of the gate driver unit at an a-th stage, a gate of the first reset transistor of the pixel circuit in the b-th row of the sub-pixel rows is connected to the first signal output terminal of the gate driver unit at a b-th stage, and a gate of the second reset transistor of the pixel circuit in the b-th row of the sub-pixel rows is connected to the first signal output terminal of the gate driver unit at a c-th stage;
wherein a is greater than b, b is greater than c, and a, b, and c are positive integers,
wherein a first control signal is output from the first signal output terminal and a second control signal is output from the second signal output terminal, and
wherein in one of scan frames of the gate driver circuit, a start time of the first control signal of the gate driver unit at the b-th stage is between a start time and an end time of the first control signal of the gate driver unit at the c-th stage, and a start time of the second control signal of the gate driver unit at the a-th stage is after an end time of the first control signal of the gate driver unit at the b-th stage.