US 12,361,808 B2
Tamper sensor for 3-dimensional die stack
Thomas Paul Leboeuf, Sandia Park, NM (US); James Anderson, Madison, AL (US); James D. Wesselkamper, Albuquerque, NM (US); and Jason J. Moore, Albuquerque, NM (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 28, 2023, as Appl. No. 18/374,639.
Prior Publication US 2025/0111765 A1, Apr. 3, 2025
Int. Cl. G08B 13/22 (2006.01); G11C 19/28 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC G08B 13/22 (2013.01) [G11C 19/287 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit die stack comprising:
a first integrated circuit die comprising a sensor network that extends substantially across an entire top surface of the first integrated circuit die; and
a second integrated circuit die stacked below the first integrated circuit die and configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias that are coupled with the first integrated circuit die and the second integrated circuit die.