US 12,361,269 B2
LSTM circuit with selective input computation
Ram Krishnamurthy, Portland, OR (US); Gregory K. Chen, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); Phil Knag, Hillsboro, OR (US); and Huseyin Ekin Sumbul, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 24, 2023, as Appl. No. 18/237,887.
Application 18/237,887 is a continuation of application No. 16/583,201, filed on Sep. 25, 2019, granted, now 11,790,217.
Prior Publication US 2023/0401434 A1, Dec. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/509 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06N 3/063 (2013.01) [G06F 7/5095 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/30098 (2013.01); G06F 9/3893 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a multiply-add circuit, the multiply-add circuit comprising multiplier circuitry to determine first and second product terms for a time increment, the multiply-add circuit comprising an adder circuit to add the first and second product terms for the time increment, the multiply-add circuit comprising circuitry to use a stored product term for one of the product terms, rather than calculate the one product term, if an accumulation of differences between consecutive, preceding input values for the one product term has not reached a threshold, wherein, the multiplier circuitry explicitly calculated the stored product term for a preceding time increment.