| CPC G06F 21/54 (2013.01) [G06F 9/3806 (2013.01); G06F 21/556 (2013.01); G06F 21/75 (2013.01); G06F 2207/7219 (2013.01)] | 20 Claims |

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1. A processor, comprising:
an authentication circuit configured to authenticate instruction operands; and
an execution circuit configured to speculatively execute, responsive to an unresolved condition, an instruction stream comprising a plurality of instructions including an instruction comprising authentication of an instruction operand, wherein to speculatively execute the instruction stream the execution circuit is configured to:
perform, using the authorization circuit, the authentication of the instruction operand, as part of speculatively executing the instruction, to generate an authentication result;
continue speculative execution of the instruction stream to generate an observable state of the processor independent of the generated authentication result, wherein to continue speculative execution the execution circuit is configured to:
complete speculative execution of the instruction; and
speculatively execute at least one additional instruction of the plurality of instructions subsequent to completing speculative execution of the instruction; and
defer reporting the generated authentication result until resolution of the condition.
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