US 12,360,904 B2
Fast synchronization mechanism for heterogeneous computing
Hsing-Chuang Liu, Hsinchu (TW); Yu-Shu Chen, Hsinchu (TW); and Hong-Yi Chen, Hsinchu (TW)
Assigned to MediaTek Inc., Hsinchu (TW)
Filed by MediaTek Inc., Hsinchu (TW)
Filed on Sep. 25, 2023, as Appl. No. 18/473,514.
Prior Publication US 2025/0103498 A1, Mar. 27, 2025
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/0808 (2016.01); G06F 12/0815 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0831 (2013.01) [G06F 12/0284 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0833 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A heterogeneous computing system operative to perform data synchronization, comprising:
a system memory;
a cluster coupled to the system memory via a system bus, the cluster including a sync circuit, a plurality of inner processors, and a snoop filter coupled to the sync circuit and the inner processors, wherein the snoop filter records addresses of cache lines owned by the inner processors in the cluster; and
a central processing unit (CPU) outside the cluster and coupled to the cluster and the system memory via the system bus, wherein the CPU is operative to send a sync command to a designated one of the inner processors, the sync command indicating a sync address range and one or more target inner processors in the cluster;
wherein the designated inner processor configures the sync circuit according to the sync command, the sync circuit operative to:
compare each address recorded in the snoop filter and owned by the one or more target inner processors with the sync address range; and
in response to a determination that a recorded address falls within the sync address range, notify a target inner processor that owns a cache line having the recorded address to take a sync action on the cache line.