US 12,360,899 B2
Scoreboard for register data cache
Winnie W. Yeung, San Jose, CA (US); Zelin Zhang, San Jose, CA (US); Cheng Li, Sunnyvale, CA (US); Hungse Cha, Campbell, CA (US); and Leela Kishore Kothamasu, Fremont, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 11, 2024, as Appl. No. 18/410,413.
Claims priority of provisional application 63/585,265, filed on Sep. 26, 2023.
Prior Publication US 2025/0103493 A1, Mar. 27, 2025
Int. Cl. G06F 12/0811 (2016.01); G06F 12/12 (2016.01); G06F 12/126 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/12 (2013.01); G06F 12/126 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
datapath circuitry configured to execute instructions that operate on input operands from architectural registers;
data cache circuitry configured to cache architectural register data for the datapath circuitry;
one or more backing caches or memories configured to store architectural register data evicted from the data cache circuitry;
scoreboard circuitry configured to track, for a given architectural register:
map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry; and
a pointer to the entry of the data cache circuitry.