US 12,360,897 B2
Systems and methods to flush data in persistent memory region to non-volatile memory using auxiliary processor
Ravi Mysore Shantamurthy, Bothell, WA (US); Mallik Bulusu, Bellevue, WA (US); Tom Long Nguyen, Auburn, WA (US); Muhammad Ashfaq Ahmed, Redmond, WA (US); and Madhav Himanshubhai Pandya, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Apr. 15, 2024, as Appl. No. 18/635,949.
Application 18/635,949 is a continuation of application No. 17/406,961, filed on Aug. 19, 2021, granted, now 11,983,111.
Prior Publication US 2024/0264941 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 12/0804 (2016.01); G06F 13/40 (2006.01); G06F 11/16 (2006.01)
CPC G06F 12/0804 (2013.01) [G06F 11/2053 (2013.01); G06F 13/4027 (2013.01); G06F 11/1612 (2013.01); G06F 2212/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing system, comprising:
volatile memory comprising a persistent memory region;
non-volatile memory; and
a system on a chip (SoC) being implemented on an integrated circuit, the SOC comprising:
a main processor on the integrated circuit that is communicatively coupled to both the volatile memory and the non-volatile memory;
an auxiliary processor on the integrated circuit;
a bridge on the integrated circuit coupled between (1) the main processor and the auxiliary processor and (2) the volatile memory and the non-volatile memory, wherein the main processor and the auxiliary processor are communicatively coupled to both the volatile memory and the non-volatile memory via the bridge; and
instructions that are executable by the auxiliary processor to cause data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory via the bridge in response to the auxiliary processor detecting a failure of the main processor.