| CPC G06F 9/30145 (2013.01) [G06F 9/3836 (2013.01)] | 16 Claims |

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1. A data processing apparatus comprising:
processing circuitry configured to execute processing instructions having an instruction order to generate one or more rows and/or one or more columns of an n×m matrix using a storage array having an n×m array of storage elements to hold one or more values generated by the instruction execution, where n and m are respective integers greater than one, each processing instruction defining one or more architectural registers to store one or more source operands, the processing circuitry comprising:
a set of physical registers;
instruction decoder circuitry configured to decode processing instructions;
detector circuitry configured to detect a groups of instructions having a maximum of one instruction of that group of instructions that writes to a given storage element;
instruction issue circuitry configured to issue decoded instructions for execution; and
instruction execution circuitry configured to execute instructions decoded by the instruction decoder circuitry, the instruction execution circuitry being configured to execute a decoded instruction by reference to one or more source operands stored by the set of architectural registers and to hold one or more values generated by that decoded instruction, the instruction execution circuitry comprising:
the storage array; and
out of order circuitry configured to selectively provide out of order execution of the group of processing instructions detected by the detector circuitry.
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