US 12,360,749 B2
Streaming data to multi-tile processing system
Daniel John Pelham Wilkinson, Bristol (GB); Richard Osborne, Bristol (GB); Graham Bernard Cunningham, Wiltshire (GB); Kenneth Gordon, London (GB); Samuel Alexander Webster, Cambridge (GB); Stavros Volos, Cambridge (GB); Kapil Vaswani, Karnataka (IN); Balaji Vembu, Redmond, WA (US); and Cédric Alain Marie Fournet, Cambridge (GB)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 18/005,246
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Jul. 13, 2021, PCT No. PCT/US2021/041502
§ 371(c)(1), (2) Date Jan. 12, 2023,
PCT Pub. No. WO2022/015775, PCT Pub. Date Jan. 20, 2022.
Claims priority of application No. 2010816 (GB), filed on Jul. 14, 2020; and application No. 2010823 (GB), filed on Jul. 14, 2020.
Prior Publication US 2023/0342121 A1, Oct. 26, 2023
Int. Cl. G06F 8/41 (2018.01)
CPC G06F 8/41 (2013.01) 19 Claims
OG exemplary drawing
 
1. A processing system comprising:
a chip comprising a plurality of tiles, each tile comprising a respective processing unit and memory storing a codelet;
an encryption unit configured to encrypt and decrypt data transferred between the tiles and a trusted computing entity via an external memory;
wherein the codelets have been compiled by a compiler at the trusted computing entity to instruct one of the tiles to transfer the encrypted data by reading from and writing to a memory region at the external memory such that a stream of encrypted data is formed, the stream using the memory region at the external memory; and
wherein the encryption unit comprises a register, and wherein the processing system comprises a secure microcontroller unit (SMCU) configured to receive a key manifest from the compiler and to use the key manifest to program the register in order that the encryption unit operates to encrypt and decrypt the data of the stream.