US 12,360,699 B2
Memory system
Haruka Mori, Kawasaki Kanagawa (JP); and Mitsunori Tadokoro, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 23, 2024, as Appl. No. 18/586,342.
Claims priority of application No. 2023-038661 (JP), filed on Mar. 13, 2023.
Prior Publication US 2024/0311039 A1, Sep. 19, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 18 Claims
OG exemplary drawing
 
13. A method of executing processes according to requests from a host in a memory system communicating with the host, wherein the memory system includes a plurality of memory chips capable of operating in parallel, a random access memory including a physical channel region in which requests issued from the host are stored and a plurality of virtual channel regions, each of which corresponds to one of a plurality of processes executed on the plurality of memory chips according to the one or more requests, and a controller configured to store the requests issued from the host in the physical channel region in order of acquisition from the host and to store an entry for each of the requests in one of the plurality of virtual channel regions, said method comprising:
determining a required degree of parallelism of the plurality of processes;
in response to determining that the required degree of parallelism is less than a predetermined threshold, selecting a next request to be executed, using the physical channel region; and
in response to determining that the required degree of parallelism is greater than or equal to the predetermined threshold, selecting the next request to be executed, using one of the plurality of virtual channel regions.