US 12,360,698 B2
Implicit ordered command handling
Huachen Li, Shanghai (CN); Zhou Zhou, Shanghai (CN); Chaofeng Zhang, Shanghai (CN); Jianfeng Li, Shanghai (CN); Chen Huang, Shanghai (CN); Lin Huang, Shanghai (CN); and Wei Li, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 25, 2024, as Appl. No. 18/646,025.
Application 18/646,025 is a continuation of application No. 17/283,210, granted, now 11,995,337, previously published as PCT/CN2021/076691, filed on Feb. 18, 2021.
Prior Publication US 2024/0345759 A1, Oct. 17, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a first command and a second command, wherein the first command indicates a first operation associated with one or more first addresses of an address space of a memory device of the one or more memory devices and the second command indicates a second operation associated with one or more second addresses of the address space of the memory device;
receive one or more first parameters associated with performing the first operation associated with the one or more first addresses of the address space; and
transmit, during a duration that at least partially overlaps with receiving the one or more first parameters, a request for one or more second parameters associated with performing the second operation associated with the one or more second addresses of the address space.