US 12,035,643 B2
Electronic component manufacturing method
Yann Canvel, Grenoble (FR); Sebastien Lagrasta, La Terrasse (FR); Sebastien Barnola, Grenoble (FR); and Christelle Boixaderas, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Sep. 28, 2021, as Appl. No. 17/488,026.
Application 17/488,026 is a continuation of application No. 16/578,022, filed on Sep. 20, 2019, granted, now 11,152,570.
Claims priority of application No. 1858603 (FR), filed on Sep. 21, 2018.
Prior Publication US 2022/0020924 A1, Jan. 20, 2022
Int. Cl. H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/063 (2023.02) [H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a mask on a stack including a layer of phase change material on a resistive layer and a conductive layer on the layer of phase change material configured to store data by switching between a crystalline phase and an amorphous phase;
patterning the layer of phase change material by etching the layer of phase change material and the conductive layer in the presence of the mask;
depositing a first passivation layer on a sidewall of the layer of phase change material after patterning the layer of phase change material;
etching the resistive layer below the first passivation layer while the first passivation layer is on the sidewall of the layer of phase change material;
removing the mask while the first passivation layer is present on the sidewall of the layer of phase change material; and
depositing a second passivation layer on the first passivation layer and on a sidewall of the resistive layer after removing the mask.