US 12,035,543 B2
Cross-point memory array with access lines
Hernan A. Castro, Shingle Springs, CA (US); Stephen H. Tang, Fremont, CA (US); and Stephen W. Russell, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 6, 2020, as Appl. No. 17/064,099.
Application 17/064,099 is a division of application No. 15/961,540, filed on Apr. 24, 2018, granted, now 10,825,867.
Prior Publication US 2021/0098531 A1, Apr. 1, 2021
Int. Cl. H10B 63/00 (2023.01); H10B 53/20 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/845 (2023.02) [H10B 53/20 (2023.02); H10B 63/20 (2023.02); H10B 63/22 (2023.02); H10B 63/24 (2023.02); H10B 63/80 (2023.02); H10B 63/84 (2023.02); H10N 70/235 (2023.02); H10N 70/245 (2023.02)] 19 Claims
OG exemplary drawing
 
12. An apparatus, comprising:
a stack that includes an electrode layer and a memory layer;
a conductive element in contact with the stack;
a conductive plug that extends through the stack and is coupled with the conductive element, the conductive plug having a first width at the memory layer and a second width at the electrode layer, the second width larger than the first width;
a first electrode at the electrode layer, the first electrode coupled with the conductive plug; and
a conformal liner at a second electrode layer within the stack, the conformal liner interposed between the conductive plug and a dielectric material.