| CPC H10B 61/22 (2023.02) [H10B 20/20 (2023.02)] | 20 Claims |
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1. A magnetic memory device comprising:
a plurality of first bit lines and a plurality of second bit lines;
a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines;
a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first cell structure in a first region, the plurality of first memory cells each comprising a first memory device and a first selection transistor; and
a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second cell structure in a second region, the plurality of second memory cells each comprising a second memory device and a second selection transistor,
wherein each of the first memory device and the second memory device comprises a magnetic tunnel junction comprising a pinned layer, a tunnel barrier layer, and a free layer,
wherein the magnetic tunnel junction in one or more of the second memory devices is configured to provide an irreversible resistance state in which the tunnel barrier layer is insulation-broken, and
wherein the first and second cell structures differ, and the plurality of first source lines extend perpendicular to the plurality of second source lines.
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