US 12,035,535 B2
Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture
Adarsh Rajashekhar, Santa Clara, CA (US); Raghuveer S. Makala, Campbell, CA (US); and Rahul Sharangpani, Fremont, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Apr. 22, 2021, as Appl. No. 17/237,447.
Application 17/237,447 is a continuation in part of application No. 16/728,825, filed on Dec. 27, 2019, granted, now 11,114,534.
Prior Publication US 2021/0242241 A1, Aug. 5, 2021
Int. Cl. H10B 51/20 (2023.01); H01L 29/76 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/24 (2006.01)
CPC H10B 51/20 (2023.02) [H01L 29/7606 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 29/16 (2013.01); H01L 29/1606 (2013.01); H01L 29/161 (2013.01); H01L 29/2003 (2013.01); H01L 29/24 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of source layers and drain layers located over a substrate;
a memory opening vertically extending through the alternating stack;
a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack;
discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers; and
a vertical stack of discrete memory material portions laterally surrounding the vertical word line;
wherein each of the discrete semiconductor channels comprises a semiconductor channel layer including a cylindrical channel portion, an upper horizontally-extending portion adjoined to a top end of the cylindrical channel portion, and a lower horizontally-extending portion adjoined to a bottom end of the cylindrical channel portion.