US 12,035,533 B2
Semiconductor memory device and manufacturing method of semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 11, 2021, as Appl. No. 17/317,289.
Claims priority of application No. 10-2020-0148724 (KR), filed on Nov. 9, 2020.
Prior Publication US 2022/0149053 A1, May 12, 2022
Int. Cl. H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked;
a first channel structure penetrating the gate stack structure;
a first contact structure connected to the first channel structure, the first contact structure extending onto the gate stack structure;
a bit line disposed on the first contact structure and being in contact with the first contact structure;
a tunnel insulating layer disposed between the first channel structure and the gate stack structure;
a data storage layer disposed between the tunnel insulating layer and the gate stack structure; and
a blocking insulating layer disposed between the data storage layer and the gate stack structure, the blocking insulating layer extending between the first contact structure and the gate stack structure,
wherein a distance between the bit line and the tunnel insulating layer is greater than a distance between the bit line and the blocking insulating layer.