US 12,035,530 B2
Three-dimensional memory devices having through stair contacts and methods for forming the same
Qinxiang Wei, Wuhan (CN); Jianhua Sun, Wuhan (CN); and Ji Xia, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 28, 2023, as Appl. No. 18/374,507.
Application 18/374,507 is a continuation of application No. 18/201,660, filed on May 24, 2023, abandoned.
Application 18/201,660 is a continuation of application No. 17/097,635, filed on Nov. 13, 2020, granted, now 11,716,846.
Application 17/097,635 is a continuation of application No. 16/292,268, filed on Mar. 4, 2019, granted, now 10,847,539.
Application 16/292,268 is a continuation of application No. PCT/CN2019/070009, filed on Jan. 2, 2019.
Prior Publication US 2024/0023333 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 29/40117 (2019.08); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers, wherein the memory stack comprises stairs in a staircase region; and
a through stair contact (TSC) extending through the memory stack in the staircase region, wherein the TSC comprises a first conductor layer and a first spacer circumscribing the first conductor layer, and the first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.