	US 12,035,528 B2
	Semiconductor device
Seung Jun Shin, Yongin-si (KR); Hyun Mog Park, Seoul (KR); and Joong Shik Shin, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 5, 2021, as Appl. No. 17/394,499.
Application 17/394,499 is a continuation of application No. 16/892,384, filed on Jun. 4, 2020, granted, now 11,114,463.
Application 16/892,384 is a continuation of application No. 15/933,544, filed on Mar. 23, 2018, granted, now 10,680,007, issued on Jun. 9, 2020.
Claims priority of application No. 10-2017-0090804 (KR), filed on Jul. 18, 2017.
Prior Publication US 2021/0366928 A1, Nov. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)

CPC H10B 43/27 (2023.02) [H01L 21/3213 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/41775 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)]

19 Claims

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

gate electrodes stacked perpendicularly on an upper surface of the substrate in the first region, the gate electrodes extending to different lengths in a first direction in the second region, and each of the gate electrodes including:

subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and

a gate connection portion connecting to each other subgate electrodes at a same level;

channels extending through the gate electrodes perpendicularly to the upper surface of the substrate in the first region; and

dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including:

first dummy channels arranged in the second region in rows and columns, the rows extending in the first direction, and the columns extending in the second direction, and

a second dummy channel passing through the gate connection portion in the second region, the second dummy channel being arranged between two columns of the first dummy channels that are adjacent to each other along the first direction,

wherein the first region is a memory cell region including a plurality of memory cells along the channels, and the second region electrically connects the memory cell region and a control logic region driving the plurality of memory cells.