US 12,035,527 B2
Semiconductor device and method for fabricating the same
Yoo Hyun Noh, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 13, 2021, as Appl. No. 17/374,772.
Claims priority of application No. 10-2021-0013498 (KR), filed on Jan. 29, 2021.
Prior Publication US 2022/0246638 A1, Aug. 4, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a lower structure including an interconnection;
forming a first contact plug coupled to the interconnection;
forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure;
forming an opening that penetrates the alternating stack and exposes the first contact plug;
forming a sacrificial plug including a void in the opening;
forming a contact hole that exposes the first contact plug by etching a portion of the sacrificial plug; and
forming a second contact plug in the contact hole,
wherein forming the sacrificial plug including the void in the opening includes:
forming a non-conformal layer that covers a top corner of the opening; and
forming a conformal layer that fills the opening over the non-conformal layer, wherein the conformal layer is formed with a void which is positioned inside the opening.