US 12,035,518 B2
Non-interleaving N-well and P-well pickup region design for IC devices
Ka-Hing Fung, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/871,603.
Application 17/871,603 is a division of application No. 17/011,440, filed on Sep. 3, 2020, granted, now 11,469,238.
Claims priority of provisional application 62/906,459, filed on Sep. 26, 2019.
Prior Publication US 2022/0375943 A1, Nov. 24, 2022
Int. Cl. H01L 27/11 (2006.01); G06F 30/392 (2020.01); G11C 11/412 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [G06F 30/392 (2020.01); G11C 11/412 (2013.01); H01L 27/0924 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
accessing an original Integrated Circuit (IC) layout design, the IC layout design including a plurality of n-type field effect transistor (NFET) regions, a plurality of p-type field effect transistor (PFET) regions, a plurality of N-well pickup regions, and a plurality of P-well pickup regions; and
generating, based on the original IC layout design, a new IC layout design, wherein the new IC layout design is generated at least in part by substituting a first subset of the N-well pickup regions and a first subset of the P-well pickup regions with a continuous N-well pickup region, and by substituting a second subset of the N-well pickup regions and a second subset of the P-well pickup regions with a continuous P-well pickup region.