US 12,035,466 B2
Systems and methods for manufacturing thin substrate
Mark J. Beesley, Carmel Valley, CA (US); Meng Chi Lee, Los Altos, CA (US); Nima Shahidi, San Francisco, CA (US); Hao Shi, Mountain View, CA (US); and Quan Qi, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 21, 2021, as Appl. No. 17/236,883.
Claims priority of provisional application 63/083,675, filed on Sep. 25, 2020.
Prior Publication US 2022/0104346 A1, Mar. 31, 2022
Int. Cl. H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/05 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/0298 (2013.01) [H05K 1/0313 (2013.01); H05K 1/05 (2013.01); H05K 1/09 (2013.01); H05K 1/11 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A multi-layered board, comprising:
a copper substrate; and
a bilayer dielectric, wherein the bilayer dielectric comprises:
a C-stage epoxy layer, wherein the C-stage epoxy layer is fully cross-linked and coupled to the copper substrate, wherein the C-stage epoxy layer comprises an amount of contamination of 1000 conductive materials per cubic meter or less; and
a B-stage epoxy layer, wherein the B-stage epoxy layer is partially cross-linked, wherein the B-stage epoxy layer is configured to transform into the C-stage epoxy layer via lamination of the B-stage epoxy layer and one or more copper traces, wherein the lamination comprises the B-stage epoxy layer being coupled to the one or more copper traces, and wherein the C-stage epoxy layer has a lower amount of contamination than the B-stage epoxy layer.