US 12,035,450 B2
Laminar electrostatic eliminator circuit for eliminating static electricity in a space
Wenkui Zhang, Guangdong (CN)
Assigned to SHENZHEN KESD TECHNOLOGY CO., LTD, Guangdong (CN)
Appl. No. 17/632,121
Filed by SHENZHEN KESD TECHNOLOGY CO., LTD, Guangdong (CN)
PCT Filed Sep. 14, 2021, PCT No. PCT/CN2021/118351
§ 371(c)(1), (2) Date Feb. 1, 2022,
PCT Pub. No. WO2022/057801, PCT Pub. Date Mar. 24, 2022.
Claims priority of application No. 202010911009.3 (CN), filed on Sep. 16, 2020.
Prior Publication US 2023/0363072 A1, Nov. 9, 2023
Int. Cl. H05F 3/04 (2006.01); H02M 3/335 (2006.01); H05F 3/02 (2006.01)
CPC H05F 3/04 (2013.01) [H02M 3/33507 (2013.01); H05F 3/02 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A laminar electrostatic eliminator circuit, comprising a main control module, a control instruction sending unit, a first driving circuit, a first boost circuit, a second driving circuit, and a second boost circuit, wherein a signal input terminal of the main control module is connected to an instruction sending terminal of the control instruction sending unit, a first control terminal and a second control terminal of the main control module are connected to an input terminal of the first driving circuit and an input terminal of the second driving circuit respectively, an output terminal of the first driving circuit is connected to an input terminal of the first boost circuit, and an output terminal of the first boost circuit is connected to a positive high voltage terminal output; and an output terminal of the second driving circuit is connected to an input terminal of the second boost circuit, and an output terminal of the second boost circuit is connected to a negative high voltage terminal output, wherein the control instruction sending unit comprises a pin header J1, a resistor R1, a resistor R2, and a resistor R3, a pin 1 of the pin header J1 is connected to a negative-high-voltage generating control signal terminal input, and is connected to an input terminal of the resistor R3, an output terminal of the resistor R3 is connected to an input terminal of the resistor R2, and is connected to a pin 4 of the pin header J1, an output terminal of the resistor R2 is connected to a pin 24 of the chip U1 as a main control chip of the main control module, and is connected to an input terminal of a capacitor C1, an output terminal of the capacitor C1 is grounded, and a pin 2 of the pin header J1 is connected to a positive-high-voltage generating control signal terminal input.