CPC H04W 52/0229 (2013.01) [H04W 76/27 (2018.02); H04W 76/28 (2018.02)] | 17 Claims |
1. A baseband processor configured to perform operations comprising:
receiving configuration information corresponding to a reference signal that is to be transmitted to a user equipment (UE) when the UE is in a first operating state;
receiving the reference signal from a cell of a network when the UE is in the first operating state;
performing one of frequency and timing tracking or automatic gain control (AGC) using the reference signal;
receiving a list of slot offsets relative to downlink control information (DCI) and the reference signal, wherein the list of slot offsets is received in a radio resource control (RRC) message;
receiving the DCI prior to receiving the reference signal when the UE is operating in an RRC connected state, wherein the DCI and the reference signal are separated by one of the slot offsets included in the list of slot offsets; and
receiving a signal from the cell during a time window that the UE is scheduled to utilize an active mode of data exchange processing.
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