US 12,034,575 B2
Clock and data recovery circuit and feed forward equalizer decoupling
Hananel Faig, Jerusalem (IL); Yair Yakoby, Kfar Shmuel (IL); and Oz Harel, Ness Ziona (IL)
Assigned to Mellanox Technologies, Ltd., Yokneam (IL)
Filed by Mellanox Technologies, Ltd., Yokneam (IL)
Filed on Dec. 12, 2022, as Appl. No. 18/079,304.
Prior Publication US 2024/0195663 A1, Jun. 13, 2024
Int. Cl. H04L 25/03 (2006.01)
CPC H04L 25/03885 (2013.01) [H04L 25/03273 (2013.01); H04L 25/03853 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver comprising:
an analog-to-digital converter (ADC) to generate a digital output comprising a set of bits corresponding to a received signal;
a calculator circuit, coupled to the ADC, the calculator circuit to:
calculate a set of tap coefficient gradient values corresponding to the digital output;
generate a first feedback signal corresponding to the set of tap coefficient gradient values; and
generate a second feedback signal corresponding to the set of tap coefficient gradient values;
a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a parameter of the received signal based on the first feedback signal; and
a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system comprises a plurality of filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.