US 12,034,469 B2
Variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus
Lalan Jee Mishra, San Diego, CA (US); Richard Dominic Wietfeldt, San Diego, CA (US); Umesh Srikantiah, San Diego, CA (US); and Karthik Manivannan, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 18, 2020, as Appl. No. 17/127,709.
Prior Publication US 2022/0200650 A1, Jun. 23, 2022
Int. Cl. H04W 48/18 (2009.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H04B 1/401 (2015.01); H04W 88/06 (2009.01)
CPC H04B 1/401 (2013.01) [G06F 13/4027 (2013.01); G06F 13/4291 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a two-wire bus interface coupled to a two-wire bus;
a clock source operative to produce a clock signal having a clock cycle, the clock source producing a clock tick once per clock cycle; and
a control circuit configured to:
set a stride length comprising a plurality of clock cycles; and
send only one clock tick from the clock source through the two-wire bus interface per stride length.