CPC H03M 3/344 (2013.01) [H03M 3/50 (2013.01)] | 16 Claims |
1. A fractional phase locked loop comprising:
a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock;
a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock;
a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise; and
a digital-to-time converter configured to
receive a cancellation code from an integrator in the sigma-delta modulator; and
cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock, and
the digital-to-time converter comprising
a cancellation circuit configured to phase align and cancel the sigma-delta modulator quantization noise with the cancellation code to generate an output, the cancellation circuit having a convergence point based on setting a resistor-capacitor constant to a controlled oscillator target period and implementing to a defined voltage; and
a cancellation point adjustment circuit configured to compensate for voltage based changes in the convergence point by comparing the output of the cancellation circuit with a reference voltage which tracks the voltage based changes,
wherein the voltage based changes are tracked using a least means square algorithm which uses a statistical output from the digital filter.
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