US 12,034,459 B2
Memory controller, memory system, and memory control method
Riki Suzuki, Yokohama (JP); Toshikatsu Hida, Yokohama (JP); Osamu Torii, Setagaya (JP); Hiroshi Yao, Yokohama (JP); and Kiyotaka Iwasaki, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 5, 2023, as Appl. No. 18/312,834.
Application 18/312,834 is a continuation of application No. 17/178,604, filed on Feb. 18, 2021, granted, now 11,683,053.
Application 17/178,604 is a continuation of application No. 16/419,717, filed on May 22, 2019, granted, now 10,965,324, issued on Mar. 30, 2021.
Application 16/419,717 is a continuation of application No. 15/341,580, filed on Nov. 2, 2016, granted, now 10,432,231, issued on Oct. 1, 2019.
Application 15/341,580 is a continuation of application No. 14/446,463, filed on Jul. 30, 2014, granted, now 9,520,901, issued on Dec. 13, 2016.
Claims priority of provisional application 61/948,788, filed on Mar. 6, 2014.
Prior Publication US 2023/0275601 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/35 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11B 20/18 (2006.01); G11C 29/52 (2006.01); H03M 13/29 (2006.01); G11C 7/10 (2006.01); G11C 29/04 (2006.01)
CPC H03M 13/35 (2013.01) [G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/1008 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/1076 (2013.01); G11C 29/52 (2013.01); H03M 13/29 (2013.01); H03M 13/2906 (2013.01); H03M 13/2957 (2013.01); G11B 20/1833 (2013.01); G11C 7/1006 (2013.01); G11C 2029/0411 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory that includes a plurality of memory areas, the plurality of memory areas including at least a first memory area and a second memory area; and
a controller configured to:
manage a level of wear of each of the plurality of memory areas;
in response to the level of wear of the first memory area being lower than a first threshold,
determine to use a first encoding method for encoding a first size of first data to generate a second size of a first parity for correcting an error in the first data such that a sum of the first size and the second size is equal to a size of each of the plurality of memory areas,
encode the first data to generate the first parity, and
write the first data and the first parity into the first memory area; and
in response to the level of wear of the second memory area being higher than or equal to the first threshold,
determine to use a second encoding method for encoding a third size of second data to generate a fourth size of a second parity for correcting an error in the second data such that the third size is smaller than the first size, and a sum of the third size and the fourth size is equal to the size of each of the plurality of memory areas,
encode the second data to generate the second parity, and
write the second data and the second parity into the second memory area.