US 12,034,458 B1
Throughput efficient Reed-Solomon forward error correction decoding
Venugopal Santhanam, Karnataka (IN); and Aman Mishra, Karnataka (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jul. 20, 2023, as Appl. No. 18/224,403.
Application 18/224,403 is a division of application No. 17/809,715, filed on Jun. 29, 2022, granted, now 11,750,222.
Int. Cl. H03M 13/00 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/1515 (2013.01) [H03M 13/1575 (2013.01); H03M 13/6516 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a first portion of a first codeword during a plurality of first non-overlap clock cycles;
receiving, by a Reed-Solomon decoder circuit, a second portion of the first codeword and a first portion of a second codeword during an overlap clock cycle between the first plurality of non-overlap clock cycles and a second plurality of non-overlap clock cycles;
receiving a second portion of the second codeword over the second plurality of non-overlap clock cycles; and
computing, by the Reed-Solomon decoder circuit, a first decoded message and a second decoded message from the first codeword and the second codeword, the first decoded message and the second decoded message being output during a period having a length equal to a sum of the first plurality of non-overlap clock cycles, the overlap clock cycle, and the second plurality of non-overlap clock cycles.